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| www.fairchildsemi.com FAN8400D (FAN8400BD3) 3-Phase BLDC Motor Driver with PLL Features * * * * * * * 3-Phase BLDC motor driver IC with speed control Phase Locked Loop (PLL) speed control Built-in phase locked detector output Current linear drive scheme External clock for arbitrary motor speed Built-in FG amplifier and integrating amplifier Auto Gain Control (AGC) circuit for compensation hall amplifier * Built-in protection circuits (over-current limit, under voltage limit, thermal shut down) Description The FAN8400D is a monolithic integrated circuit. it is one driver for laser beam printer (LBP) polygon mirror motor, which has single chip implementation of all circuits. For extremely high rotational precision, it employs the phase locked loop (PLL) speed control scheme. 28-SSOPH-375SG2 Typical application * * * * * Polygon mirror motor drive IC for laser beam printer Polygon mirror motor drive IC for facsimile Polygon mirror motor drive IC for duplicator Polygon mirror motor drive IC for multi function printer General 3 phase BLDC motor drive IC Ordering Information Device FAN8400BD3 Package 28-SSOPH-375SG2 Operating Temp -20C ~ +80C -20C ~ +80C FAN8400BD3TF 28-SSOPH-375SG2 Rev.1.0.1 (c)2001 Fairchild Semiconductor Corporation FAN8400D (FAN8400BD3) Pin Assignments AGC FGINFGS FGOUT S/S NC NC 1 2 3 4 5 6 7 28 27 26 25 24 23 22 HWHW+ HUHU+ HVHV+ W FIN FAN8400D FIN SGND LD ECLK PD EI EO FC 8 9 10 11 12 13 14 21 20 19 18 17 16 15 V U RF PGND VCC VREG NC 2 FAN8400D (FAN8400BD3) Pin Definitions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name AGC FGINFGS FGOUT S/S NC NC SGND LD ECLK PD EI EO FC NC VREG VCC PGND RF U V W HV+ HVHU+ HUHW+ HWSignal ground Phase locked loop detector output External clock Phase locked loop detector output Error amplifier inverting input Error amplifier output Control amplifier frequency correction Regulator voltage stabilization output Power supply Power ground Output current detection U output V output W output V hall amplifier non inverting input V hall amplifier inverting input U hall amplifier non inverting input U hall amplifier inverting input W hall amplifier non inverting input W hall amplifier inverting input Pin Function Description AGC amplifier frequency characteristics correction FG amplifier inverting input FG pulse output FG amplifier output Stop and start - 3 FAN8400D (FAN8400BD3) Internal Block Diagram AGC FGINFGS FGOUT S/S NC NC 1 2 3 4 5 6 7 AGC 28 27 HWHW+ HUHU+ HVHV+ W + + VREG 2 Hall AMP Matrix 26 25 24 23 22 S/S PLL FIN Clock Output Controller FIN SGND LD ECLK PD EI EO FC 8 9 10 11 12 13 14 Lock Detector V-type Control OCL TSD & UVLO 21 20 19 18 17 Regulator 16 15 V U RF PGND VCC VREG NC + VREG 2 4 FAN8400D (FAN8400BD3) Absolute Maximum Ratings (Ta = 25C) Parameter Maximum supply voltage Maximum output current Power dissipation Operating temperature Storage temperature Symbol VCCMAX IOMAX Pd TOPR TSTG Value 30 0.6 1.7 -20 ~ +80 -50 ~ +150 Unit V A W C C Remark - Recommended Operating Conditions (Ta = 25C) Parameter Operating voltage range Symbol VCC Min. 20 Typ. 24 Max. 28 Unit V 5 FAN8400D (FAN8400BD3) Electrical Characteristics (Ta = 25C) Parameter POWER SUPPLY CURRENT Low power supply current Typical power supply current High power supply current U source saturation voltage (1) U source saturation voltage (2) U sink saturation voltage (1) U sink saturation voltage (2) V source saturation voltage (1) V source saturation voltage (2) V sink saturation voltage (1) V sink saturation voltage (2) W source saturation voltage (1) W source saturation voltage (2) W sink saturation voltage (1) W sink saturation voltage (2) U output leakage current V output leakage current W output leakage current UNDER VOLTAGE LIMIT UVLO operating voltage UVLO hysteresis REGULATOR VOLTAGE OUTPUT Regulator output voltage Power supply variation Load variation HALL AMPLIFIER INPUT BLOCK HU+ hall AMP input bias current HU- hall AMP input bias current HV+ hall AMP input bias current HV- hall AMP input bias current HW+ hall AMP input bias current HW- hall AMP input bias current Hall differential input range Hall common input range IBHA1+ IBHA1- IBHA2+ IBHA2- IBHA3+ IBHA3- VHIN VICM Sine wave input Differential input : 50mVp-p 50 3.5 2 2 2 2 2 2 10 10 10 10 10 10 350 VCC-3.5 A A A A A A mVp-p V VREG HVREG1 HVREG2 VCC=20~28V ILOAD=0~10mA 5.8 6.3 6.8 100 100 V mV mV VSD HVSD 7.0 1.0 7.6 1.3 8.2 1.6 V V ICCL ICCT ICCH VSATUU1 VSATUU2 VSATUL1 VSATUL2 VSATVU1 VSATVU2 VSATVL1 VSATVL2 VSATWU1 VSATWU2 VSATWL1 VSATWL2 IOLEAKU IOLEAKV IOLEAKW Stop mode, VCC=20V Stop mode, VCC=24V Stop mode, VCC=28V IO=0.6A, RF=0 IO=0.3A, RF=0 IO=0.6A, RF=0 IO=0.3A, RF=0 IO=0.6A, RF=0 IO=0.3A, RF=0 IO=0.6A, RF=0 IO=0.3A, RF=0 IO=0.6A, RF=0 IO=0.3A, RF=0 IO=0.6A, RF=0 IO=0.3A, RF=0 VCC=28V, U=28V VCC=28V, V=28V VCC=28V, W=28V 20 21 22 30 31 32 1.8 1.6 0.5 0.25 1.8 1.6 0.5 0.25 1.8 1.6 0.5 0.25 40 41 42 2.5 2.3 1.0 0.7 2.5 2.3 1.0 0.7 2.5 2.3 1.0 0.7 100 100 100 mA mA mA V V V V V V V V V V V V A A A Symbol Conditions Min. Typ. Max. Unit OUTPUT POWER TRANSISTOR CHARACTERISTICS (VAGC = 3.5V) 6 FAN8400D (FAN8400BD3) Electrical Characteristics (Continued) Parameter FG AMPLIFIER BLOCK FG AMP. input bias current FG AMP. DC bias level FG output high level voltage FG output low level voltage FGS high / low input hysteresis FGS low / high input hysteresis FGS hysteresis FGS input operating level FGS output saturation voltage FGS output leakage current ERROR AMPLIFIER BLOCK Error AMP. input bias current Error AMP. DC bias level Error output high level voltage Error output low level voltage CURRENT LIMIT OPERATION RF output voltage limit CONTROLLER BLOCK Dead zone Output idle voltage Forward gain Reverse gain Accelerate command voltage Decelerate command voltage Forward limit voltage Reverse limit voltage PD output high level voltage PD output low level voltage PD output source current PD output sink current LD output saturation voltage LD output leakage current VDZ VID GDF+ GDF- VSTA VSTO VL+ VL- VPDH VPDL IPD+ IPD- VLDSAT ILDLEAK RF=22 RF=22 No external load No external load VPD=0.5*VREG VPD=0.5*VREG ILD=5mA VCC=28V 50 0.4 -0.6 VREG-1.1V 5.2 1.0 100 0.5 -0.5 0.8 0.60 0.60 0.1 300 5 0.6 -0.4 1.5 0.7 -0.6 0.4 10 mV mV V V V V V V mA mA V A VRF 0.55 0.60 0.65 V IBER VBER VOHER VOLER No external load No external load -1 2.90 VREG-1.1V 3.15 1 3.40 1.0 A V V V IBFG VBFG VOHFG VOLFG VSHL VSLH VFGL VFGSIL VFGSSAT IFGSLEAK IFGS=4mA VCC=28V No external load No external load -1 2.90 VREG-1.1V -50 100 100 400 3.15 0.8 0 150 0.2 1 3.40 1.2 50 200 200 0.4 10 A V V V mV mV mV mVp-p V A Symbol Conditions Min. Typ. Max. Unit FG SCHMIDT COMPARATOR BLOCK PHASE COMPARATOR OUTPUT BLOCK PHASE LOCKED LOOP DETECTOR OUTPUT BLOCK 7 FAN8400D (FAN8400BD3) Electrical Characteristics (Continued) Parameter EXTERNAL CLOCK INPUT BLOCK External input frequency ECLK input open voltage ECLK input high level current ECLK input low level current S/S BLOCK S/S input high level voltage S/S input low level voltage S/S hysteresis S/S input open voltage S/S input high level current S/S input low level current VIHSS VILSS VISSS VIOSS IIHSS IILSS VSS=VREG VSS=0V 3.0 0 0.3 3.7 100 -400 0.5 4.2 150 -300 VREG 1.5 0.7 4.7 200 -200 V V V V A A FCLK VIOCLK IIHCLK IILCLK VCLK=VREG VCLK=0V External clock mode 0.5 3.7 100 -400 4.2 150 -300 7.0 4.7 200 -200 KHz V A A Symbol Conditions Min. Typ. Max. Unit 8 FAN8400D (FAN8400BD3) Application Information 1. Output Block * * * * * * 3 Phase power transistor and free wheeling diodes Reverse active type upper side diodes and parasitic lower side diodes full wave current linear drive with current feedback Connection with external capacitor to prevent voltage spike and oscillation by current drive Output transistor commutation by "Winner takes all" method Built in over current limit (OCL) circuit 2. Hall AMP Block * Detection of rotor position using 3 phase hall sensors * Determination of output commutation by hall signal Forward torque [ Reverse torque] Hall U H H H L L L Hall V L L H H H L Hall W Output U H L L L H H L [H] L [H] M [M] H [L] H [L] M [M] Output V H [L] M [M] L [M] L [H] M [M] H [L] Output W M [M] H [L] H [L] M [M] L [H] L [H] 3. AGC Block * This block is remained output amplitude. * It is controlled by envelope through hall signals. 1 V AGC -------------------H NI - H I NOTES: VAGC is voltage of AGC output. HNI is hall non inverting input voltage. HI is hall inverting voltage. 4. Speed Control Block * Digital phase locked loop (PLL) circuit * Generating error pulse between rising edge of clock and falling edge of FG signal. * High precision stable speed control 9 FAN8400D (FAN8400BD3) 5. FG AMP & FG Schmidt Comparator Block * This block measures of motor rotation speed and controls motor speed. * It is determined FG AMP gain and filter by external component. * FG schmidt block change sine wave form to square wave form 6. Error AMP Block * * * * It composes of dumping filter and ripple filter by external component. It determines output amplitude of error AMP by width error pulse. It is determined output current by output amplitude of error AMP. Bidirectional torque control VRF Reverse Direction VDZ Forward Direction VREG/2 VEO 7. Regulator Block * Power supply of control circuits in inside. * Band gap reference circuits. 8. Lock Detector * It is low when FG frequency reaches capture range of clock frequency. * Open correct 9. FG Pulse Output * Monitoring pin for motor rotative speed * Open correct 10. Stop And Start * Stop mode: Open or high voltage * Start mode: Low voltage 10 FAN8400D (FAN8400BD3) Test Circuits VCC 3.5V 56K 0.1u + 1 2 28 27 26 25 24 23 22 + + + HV HU HW 1K 3 4 1K 5 6 7 VCC FAN8400D VCC 8 10K 9 10 VREG 11 12 13 14 20 19 21 VCC VCC 22 18 17 16 15 VCC 10u + + 0.1u 0.1u + 11 FAN8400D (FAN8400BD3) Typical Application Circuits 1 FG Sensor FGS 2 3 4 S/S 5 6 7 28 27 26 25 24 23 22 + + + HV HU HW FAN8400D M 8 LD ECLK 9 10 11 12 13 14 21 20 19 18 17 16 15 VCC + 12 FAN8400D (FAN8400BD3) 13 FAN8400D (FAN8400BD3) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 11/7/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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